====== STM32 Sleep/Wake Issues ======

Here are a bunch of mistakes I have made that resulted in STM32 not sleeping or not waking.

===== STM32 Not Sleeping =====

  * IWDG not stopping
    * Conditions:
      * Option bytes -> ''IWDG_SW'' bit: cleared (0)
      * MCU core is in Stop mode
    * Root cause:
      * Independent watchdog counter is running in Stop mode
    * Solution:
      * Option bytes -> ''IWDG_STOP'' bit: cleared (0: Independent watchdog counter is frozen in Stop mode)
      * If STM32 part does not support ''IWDG_STOP'', then you must wake the MCU before IWDG expires, reload IWDG then go back to Stop mode

===== STM32 Not Waking =====

  * RTC not waking STM32 due to alarm not programmed
    * Root cause(s) could be any of:
      * Backup domain is protected
        * Solutions:
          * If keeping backup domain locked: Call ''HAL_PWR_EnableBkUpAccess()'' to set the DBP bit in the Power control register 1 (PWR_CR1) to enable access to the backup domain before setting RTC time, alarm or backup registers
          * If keeping backup domain unlocked: Ensure ''HAL_PWR_DisableBkUpAccess()'' is not called to prevent clearing the DBP bit inadvertently
      * LSE oscillation failed during shutdown
        * Solutions:
          * Verify ''%%__HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__)%%'' is called before setting RTC clock source to LSE, to set an appropriate drive level (refer to AN2867 link below)
            * Refer to STM32 part-specific HAL user manual for valid values for ''%%__RCC_LSEDRIVE__%%"'
            * Refer to [[https://www.st.com/resource/en/application_note/an2867-guidelines-for-oscillator-design-on-stm8afals-and-stm32-mcusmpus-stmicroelectronics.pdf|AN2867 Guidelines for oscillator design on STM8AF/AL/S and STM32 MCUs/MPUs]] for drive level calculation
          * Verify LSE circuit against AN2867
          * Verify hardware pins for damage or contamination