====== Build UEFI for ClearFog CX/HoneyComb LX2 ======

===== Prerequisites =====

  * Docker on Linux
  * git
  * x86_64 or aarch64 build host
===== Steps =====

  * ''%%git clone --depth=1 --single-branch --branch docker-dubious-ownership-fix https://github.com/ndoo/lx2160a_uefi.git && cd lx2160a_uefi%%''
  * ''docker build -t lx2160a_uefi docker/''
  * ''%%docker run -e SOC_SPEED=2200 -e BUS_SPEED=800 -e DDR_SPEED=3200 -e XMP_PROFILE=1 -v "$PWD":/work:Z --rm -i -t lx2160a_uefi build%%''
  * ''ls images''
  * ''sudo dd if=images/[image name] of=/dev/[your microsd reader device]''

===== Valid Speed Settings =====

  * **SOC_SPEED: 600 to 2200 (MHz) in 100 MHz increments** (default: 2000 MHz)
    * //CGA_PLL1_RAT = CGA_PLL1_RAT = SOC_SPEED / 100//
  * **BUS_SPEED: 550 to 800 (MHz) in 100 MHz increments**, except 600 MHz (default: 700 MHz)
    * //SYS_PLL_RAT = 2 * BUS_SPEED / 100 - 1//
    * //0b01011 - 11:1 - is a reserved value//
  * **DDR_SPEED: 600 to 3200 (MHz) in 100 MHz increments**
    * //MEM_PLL_RAT = MEM2_PLL_RAT = DDR_SPEED / 100//

- //QorIQ LX2160A Reference Manual, 4.9.8.9 Reset Control Word (RCW) Register Descriptions.//

==== Anecdotal Tips ====

  * Overclocking SOC_SPEED = 2200 MHz is stable for most LX2160A; even higher speeds can be set but will be unstable
  * Overclocking BUS_SPEED = 800 MHz caused core lockups on heavy PCIe load for me
===== Other Build Options =====

  * **AMDGOP**: **(undefined)**, " "
    * Undefined: Build UEFI GOP driver (for full-resolution graphical UEFI boot)
    * " ": Do not build UEFI GOP driver
  * **BIFURPCI**: **(undefined)**, TRUE
    * Undefined: SerDes 3 protocol (SRDS_PRTCL_S3) = PCI Gen 3 x8
    * TRUE: SerDes 3 protocol (SRDS_PRTCL_S3) = PCIE Gen 3 x4 + PCIe Gen 3 x4, i.e. bifurcate the physical PCIe x16 slot from { x8, x0 } to { x4, x4, x0, x0 }
  * **BOOT_MODE**: flexspi_nor, **sd**
    * flexspi_nor: RCW at block 0
    * sd: RCW at block 8
  * **SERDES**: 4_5_2, **8_5_2**, 13_5_2, 20_5_2
    * The 3 digits correspond to SRDS_PRTCL_S1, SRDS_PRTCL_S2 and SRDS_PRTCL_S3 respectively
    * SRDS_PRTCL_S1 = 4: 8x SGMII (1 GbE) - 4 SFP & 4x1G lanes to QSFP28 cage
    * SRDS_PRTCL_S1 = 8: 8x USXGMII (10 GbE) - 4 SFP+ & 4x10G lanes to QSFP28 cage (QSFP+ PSM/quad breakout DAC)
    * SRDS_PRTCL_S1 = 13: 2x 100 GbE - 1x100G to QSFP28 cage (SFP+ cages non-functional((Maybe a 100G DAC breakout might work in reverse?!)))
    * SRDS_PRTCL_S1 = 20: 2x 40GbE - 1x40G to QSFP28 cage (SFP+ cages non-functional((Maybe a 40G DAC breakout might work in reverse?!)))
    * Other SerDes 1 protocols will not work unless you [[https://github.com/nxp-qoriq/mc-utils/tree/master/config/lx2160a/LX2160A-RDB|compile]] the [[https://github.com/SolidRun/edk2-non-osi/tree/c4f571fe0da70cafc58b90342a766da854e71572/Platform/SolidRun/LX2160aCex7/QoriqMcBinaryDtbs|necessary DPC & DPL DTB files]] and update runme.sh to support these port configs
  * **X64EMU_ENABLE**: **(undefined)**, (any value)
    * Any value: Enable emulation for amd64 UEFI OpROMs to work
  * **XMP_PROFILE**: **(undefined)**, 1, 2, ...
    * (undefined): Use JEDEC speeds
    * 1, ...: Use XMP profile at this index
    * Note that the LX2160A CEx7 COM only supplies 1.2V to the DIMMs, so XMP profiles requiring 1.35V will be unstable