Table of Contents

STM32U0 Notes

Literature

Development Boards

  1. Nucleo-U083RC (STM32U083RCT6)
  2. STM32U083C-DK (STM32U083MC)

Operating Conditions

Native USB (STM32U073, STM32U083)

In order to use the native USB for programming on pins PA11 and PA12, the following settings must be done in STM32CubeProgrammer → Option bytes → User Configuration.

Option byte name Value Description Notes
NBOOT_SEL 0 (Unchecked) BOOT0 pin (legacy mode) :!: Factory setting is 1. You must change it to 0 to keep USB DFU programming capability. :!:
nBOOT1 1 (Checked) Boot from Flash if BOOT0 = 1, otherwise System Memory This is the factory setting
NRST_MODE 1 or 3 1: Reset input only
3. Bidirectional reset: The NRST pin is configured in reset input/output (legacy) mode
3 is the factory setting

:!: Note: Native USB does not enumerate if HCLK is lower than the default 16 MHz, e.g. by adjusting the AHB prescaler. It will still work in bootloader mode for DFU, it only affects runtime usage of USB e.g. HID, CDC serial.

STM32duino LowPower & RTC

State Peripherals Memory Voltage Supplies (VDDx) STM32RTC::LSI_CLOCK STM32RTC::LSE_CLOCK :!: STM32RTC::HSE_CLOCK :!:
LowPower.idle() On On On Supported Supported Supported
LowPower.sleep() On On On Supported Supported Supported
LowPower.deepSleep() On On On Supported Supported Supported
LowPower.shutdown() :!: Off Off Off Supported

:!:: External hardware required

Prerequisites for LowPower.shutdown()

Choosing an LSE Crystal

  1. Hardware
    1. Choose a 32.768 kHz crystal oscillator3)
    2. Choose the load capacitance
      • C1 = C2 = 2 * (CL - Cstray)
      • “Stray capacitance Cstray comes from the pins of the chip and parasitics from the board. It is often approximated as 5pF.”4)
  2. Software
    1. Configure LSE drive level: __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRV__); Select the lowest value that can provide robust LSE start-up5)
      Substitute __LSEDRV__ with:
      1. RCC_LSEDRIVE_LOW
      2. RCC_LSEDRIVE_MEDIUMLOW (default if __HAL_RCC_LSEDRIVE_CONFIG is not called)
      3. RCC_LSEDRIVE_MEDIUMHIGH
      4. RCC_LSEDRIVE_HIGH
1)
RM0503, §3.7.7: FLASH option register (FLASH_OPTR), Bits 10:8 BOR_LEV[2:0]: BOR reset level
2)
DS14581/DS14548/DS14463, §6.3.7: External clock source characteristics, Low-speed external clock generated from a crystal resonator
3)
AN2867 Guidelines for oscillator design on STM8AF/AL/S and STM32 MCUs/MPUs, §5.2: STM32-compatible low-speed resonators, Table 7: Recommended crystal / MEMS resonators for the LSE oscillator in STM32 products
5)
RM0503, §5.2.6: LSE clock