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projects:electronics:stm32:stm32u0_notes [2025/03/12 16:22] – Lots more literature and information Andrew Yongprojects:electronics:stm32:stm32u0_notes [2025/06/19 07:23] (current) – [Choosing an LSE Crystal] notes about drive level and more recommendation logic Andrew Yong
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     * 1.71 ≤ VDDx ≤ 3.60 V (absolute maximum: 4.00 V)     * 1.71 ≤ VDDx ≤ 3.60 V (absolute maximum: 4.00 V)
     * Nucleo-083RC LEDs become very dim when 3.3V net falls below 1.80 V     * Nucleo-083RC LEDs become very dim when 3.3V net falls below 1.80 V
-  * Brownout Reset((RM0503, §3.7.7 FLASH option register (FLASH_OPTR), Bits 10:8 BOR_LEV[2:0]: BOR reset level))+  * Brownout Reset((RM0503, §3.7.7FLASH option register (FLASH_OPTR), Bits 10:8 BOR_LEV[2:0]: BOR reset level))
     * Selectable: 1.7, 2.0, 2.2, 2.5 or 2.8 V     * Selectable: 1.7, 2.0, 2.2, 2.5 or 2.8 V
  
 ===== Native USB (STM32U073, STM32U083) ===== ===== Native USB (STM32U073, STM32U083) =====
  
-In order to use the native USB for programming on pins PA11 and PA12, the following settings **must** be done in STM32CubeProgrammer --> Option bytes --> User Configuration.+In order to use the native USB for programming on pins PA11 and PA12, the following settings **must** be done in STM32CubeProgrammer -> Option bytes -> User Configuration.
  
 ^ Option byte name  ^ Value  ^ Description ^ Notes ^ ^ Option byte name  ^ Value  ^ Description ^ Notes ^
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 | NRST_MODE | 1 or 3 | 1: Reset input only\\ 3. Bidirectional reset: The NRST pin is configured in reset input/output (legacy) mode | 3 is the factory setting | | NRST_MODE | 1 or 3 | 1: Reset input only\\ 3. Bidirectional reset: The NRST pin is configured in reset input/output (legacy) mode | 3 is the factory setting |
  
 +:!: Note: Native USB does not enumerate if HCLK is lower than the default 16 MHz, e.g. by adjusting the AHB prescaler. It will still work in bootloader mode for DFU, it only affects runtime usage of USB e.g. HID, CDC serial.
 ===== STM32duino LowPower & RTC ===== ===== STM32duino LowPower & RTC =====
  
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 ==== Prerequisites for LowPower.shutdown() ==== ==== Prerequisites for LowPower.shutdown() ====
  
-  * External 32.768 kHz crystal for LSE((DS14581/DS14548/DS14463, §6.3.7 External clock source characteristics, Low-speed external clock generated from a crystal resonator))+  * External 32.768 kHz crystal for LSE((DS14581/DS14548/DS14463, §6.3.7External clock source characteristics, Low-speed external clock generated from a crystal resonator))
   * <code>rtc.setClockSource(STM32RTC::LSE_CLOCK);   * <code>rtc.setClockSource(STM32RTC::LSE_CLOCK);
 rtc.begin();</code> rtc.begin();</code>
  
-==== RTC Clock Sources ==== +===== Choosing an LSE Crystal =====
  
 +  - **Hardware**
 +    - Choose a **32.768 kHz crystal** from [[https://www.st.com/resource/en/application_note/an2867-guidelines-for-oscillator-design-on-stm8afals-and-stm32-mcusmpus-stmicroelectronics.pdf|AN2867 Guidelines for oscillator design on STM8AF/AL/S and STM32 MCUs/MPUs]], §5.2: STM32-compatible low-speed resonators, Table 7: Recommended crystal / MEMS resonators for the LSE oscillator in STM32 products
 +      * JLCPCB basic part: [[https://jlcpcb.com/partdetail/SeikoEpson-Q13FC13500004/C32346|Seiko Epson FC-135 32.768 KHz 12.5 pF ±20 ppm]] (I don't recommend this as 12.5pF capacitors require a high drive level and will consume more power during RTC shutdown)
 +      * A lower g<sub>mcrit</sub> value is preferable to reduce the power consumption of the LSE oscillator
 +      * A higher g<sub>mcrit</sub> value will increase power consumption but will have better frequency stability
 +    - Take note of the g<sub>mcrit</sub> value in the table of the chosen crystal
 +    - Choose the **load capacitance**
 +      * C1 = C2 = 2 * (C<sub>L</sub> - C<sub>stray</sub>)
 +      * "Stray capacitance C<sub>stray</sub> comes from the pins of the chip and parasitics from the board. It is often approximated as 5pF."(([[https://microchip.my.site.com/s/article/Calculating-crystal-load-capacitor|Calculating crystal load capacitor]]))
 +  - **Software**
 +    - Configure **LSE drive level**: ''%%__HAL_RCC_LSEDRIVE_CONFIG%%(//%%__LSEDRV__%%//)'' based on the g<sub>mcrit</sub> value
 +      - ''RCC_LSEDRIVE_LOW''
 +      - ''RCC_LSEDRIVE_MEDIUMLOW'' (default if ''%%__HAL_RCC_LSEDRIVE_CONFIG%%'' is not called)
 +      - ''RCC_LSEDRIVE_MEDIUMHIGH''
 +      - ''RCC_LSEDRIVE_HIGH''
 +      - The LSE drive level's G<sub>m_crit_max</sub> must be higher than the g<sub>mcrit</sub> value;\\ e.g. if g<sub>mcrit</sub> = 2.0, ''RCC_LSEDRIVE_HIGH'' must be used, as ''RCC_LSEDRIVE_MEDIUMHIGH'''s G<sub>m_crit_max</sub> of 1.7 was exceeded
projects/electronics/stm32/stm32u0_notes.1741796531.txt.gz · Last modified: by Andrew Yong