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--- projects:homelab:clearfog_cx_lx2:build_uefi [2024/09/30 15:43] – [Prerequisites] Andrew Yong
+++ projects:homelab:clearfog_cx_lx2:build_uefi [2024/10/01 16:47] (current) – [Valid Speed Settings] Andrew Yong
@@ Line 8: / Line 8: @@
 ===== Steps =====
-  * ''git clone --depth=1 --single-branch --branch docker-dubious-ownership-fix git@github.com:ndoo/lx2160a_uefi.git''
+  * ''%%git clone --depth=1 --single-branch --branch docker-dubious-ownership-fix https://github.com/ndoo/lx2160a_uefi.git && cd lx2160a_uefi%%''
   * ''docker build -t lx2160a_uefi docker/''
-  * ''docker run -e SOC_SPEED=2200 -e BUS_SPEED=800 -e DDR_SPEED=3200 -e XMP_PROFILE=1 -v %%"$PWD"%%:/work:Z --rm -i -t lx2160a_uefi build''
+  * ''%%docker run -e SOC_SPEED=2200 -e BUS_SPEED=800 -e DDR_SPEED=3200 -e XMP_PROFILE=1 -v "$PWD":/work:Z --rm -i -t lx2160a_uefi build%%''
   * ''ls images''
   * ''sudo dd if=images/[image name] of=/dev/[your microsd reader device]''
@@ Line 16: / Line 16: @@
 ===== Valid Speed Settings =====
-  * **SOC_SPEED: 600 to 2200 (MHz) in 100 MHz increments**
+  * **SOC_SPEED: 600 to 2200 (MHz) in 100 MHz increments** (default: 2000 MHz)
     * //CGA_PLL1_RAT = CGA_PLL1_RAT = SOC_SPEED / 100//
-  * **BUS_SPEED: 550 to 800 (MHz) in 100 MHz increments**, except 600 MHz
+  * **BUS_SPEED: 550 to 800 (MHz) in 100 MHz increments**, except 600 MHz (default: 700 MHz)
     * //SYS_PLL_RAT = 2 * BUS_SPEED / 100 - 1//
     * //0b01011 - 11:1 - is a reserved value//
@@ Line 26: / Line 26: @@
 - //QorIQ LX2160A Reference Manual, 4.9.8.9 Reset Control Word (RCW) Register Descriptions.//
+==== Anecdotal Tips ====
+  * Overclocking SOC_SPEED = 2200 MHz is stable for most LX2160A; even higher speeds can be set but will be unstable
+  * Overclocking BUS_SPEED = 800 MHz caused core lockups on heavy PCIe load for me
 ===== Other Build Options =====
+  * **AMDGOP**: **(undefined)**, " "
+    * Undefined: Build UEFI GOP driver (for full-resolution graphical UEFI boot)
+    * " ": Do not build UEFI GOP driver
   * **BIFURPCI**: **(undefined)**, TRUE
     * Undefined: SerDes 3 protocol (SRDS_PRTCL_S3) = PCI Gen 3 x8

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