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--- projects:electronics:stm32:stm32u0_notes [2025/03/29 07:11] – Choosing an LSE Crystal Andrew Yong
+++ projects:electronics:stm32:stm32u0_notes [2025/06/19 07:23] (current) – [Choosing an LSE Crystal] notes about drive level and more recommendation logic Andrew Yong
@@ Line 45: / Line 45: @@
 | NRST_MODE | 1 or 3 | 1: Reset input only\\ 3. Bidirectional reset: The NRST pin is configured in reset input/output (legacy) mode | 3 is the factory setting |
-:!: Note: Native USB does not enumerate if HCLK is lower than the default 16 MHz, e.g. by adjusting the AHB prescaler.
+:!: Note: Native USB does not enumerate if HCLK is lower than the default 16 MHz, e.g. by adjusting the AHB prescaler. It will still work in bootloader mode for DFU, it only affects runtime usage of USB e.g. HID, CDC serial.
 ===== STM32duino LowPower & RTC =====
@@ Line 65: / Line 65: @@
   - **Hardware**
-    - Choose a **crystal oscillator**(([[https://www.st.com/resource/en/application_note/an2867-guidelines-for-oscillator-design-on-stm8afals-and-stm32-mcusmpus-stmicroelectronics.pdf|AN2867 Guidelines for oscillator design on STM8AF/AL/S and STM32 MCUs/MPUs]], §5.2: STM32-compatible low-speed resonators, Table 7: Recommended crystal / MEMS resonators for the LSE oscillator in STM32 products))
+    - Choose a **32.768 kHz crystal** from [[https://www.st.com/resource/en/application_note/an2867-guidelines-for-oscillator-design-on-stm8afals-and-stm32-mcusmpus-stmicroelectronics.pdf|AN2867 Guidelines for oscillator design on STM8AF/AL/S and STM32 MCUs/MPUs]], §5.2: STM32-compatible low-speed resonators, Table 7: Recommended crystal / MEMS resonators for the LSE oscillator in STM32 products
+      * JLCPCB basic part: [[https://jlcpcb.com/partdetail/SeikoEpson-Q13FC13500004/C32346|Seiko Epson FC-135 32.768 KHz 12.5 pF ±20 ppm]] (I don't recommend this as 12.5pF capacitors require a high drive level and will consume more power during RTC shutdown)
+      * A lower g<sub>mcrit</sub> value is preferable to reduce the power consumption of the LSE oscillator
+      * A higher g<sub>mcrit</sub> value will increase power consumption but will have better frequency stability
+    - Take note of the g<sub>mcrit</sub> value in the table of the chosen crystal
     - Choose the **load capacitance**
       * C1 = C2 = 2 * (C<sub>L</sub> - C<sub>stray</sub>)
       * "Stray capacitance C<sub>stray</sub> comes from the pins of the chip and parasitics from the board. It is often approximated as 5pF."(([[https://microchip.my.site.com/s/article/Calculating-crystal-load-capacitor|Calculating crystal load capacitor]]))
   - **Software**
-    - Configure **LSE drive level**: ''%%__HAL_RCC_LSEDRIVE_CONFIG%%(//%%__LSEDRV__%%//)''; Select the lowest value that can provide robust LSE start-up((RM0503, §5.2.6: LSE clock))\\ Substitute ''//%%__LSEDRV__%%//'' substitute with:
+    - Configure **LSE drive level**: ''%%__HAL_RCC_LSEDRIVE_CONFIG%%(//%%__LSEDRV__%%//)'' based on the g<sub>mcrit</sub> value
       - ''RCC_LSEDRIVE_LOW''
       - ''RCC_LSEDRIVE_MEDIUMLOW'' (default if ''%%__HAL_RCC_LSEDRIVE_CONFIG%%'' is not called)
       - ''RCC_LSEDRIVE_MEDIUMHIGH''
       - ''RCC_LSEDRIVE_HIGH''
+      - The LSE drive level's G<sub>m_crit_max</sub> must be higher than the g<sub>mcrit</sub> value;\\ e.g. if g<sub>mcrit</sub> = 2.0, ''RCC_LSEDRIVE_HIGH'' must be used, as ''RCC_LSEDRIVE_MEDIUMHIGH'''s G<sub>m_crit_max</sub> of 1.7 was exceeded

ndoo.sg

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